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asahi kasei [AK4707] ms0551-e-00 2006/10 - 1 - general description the AK4707 offers the ideal featur es for digital set-top-box syst ems. the AK4707 includes the audio switches, video switches, et c. designed primarily for digital set-top- box systems. the AK4707 is offered in a space saving 48-pin lqfp package. features ? analog switches for scart audio section thd+n: ? 86db (@2vrms) dynamic range: 96db (@2vrms) analog inputs two full differential stereo input or single-ended input for decoder dac two stereo input (tv & vcr scart) analog outputs two stereo outputs (tv & vcr scart) pop noise free circuit for power on/off video section 75ohm driver 6db gain for outputs four cvbs/y inputs (encx2, tv, vcr) , two cvbs/y outputs (tv, vcr) three r/c inputs (encx2, vcr), one r/c output (tv) two g and b inputs (enc, vcr), one g and b outputs (tv) tv/vcr input monitor loop-through mode for standby auto-startup mode for power saving scart pin#16 (fast blanking), pin#8 (slow blanking) control ? power supply 5v+/ ? 5% and 12v+/ ? 5% low power dissipation / low power standby mode ? package small 48pin lqfp ? ak4702 pin compatible av scart switch AK4707
asahi kasei [AK4707] ms0551-e-00 2006/10 - 2 - ? block diagram tvoutl tvoutr vcroutl vcroutr tvinl t vinr vcrinl vcrinr a inl+ a inl- a inr- a inr+ bias tv1-0 mono scl sda register control pdn pvcom vd vcr1-0 vmono dvcom vp amp vss -6db to +12db (3db/step) volume #0 audio block
asahi kasei [AK4707] ms0551-e-00 2006/10 - 3 - enc c tvrc enc g/cvbs vcr g tvg enc b vcr b tvb enc y tvvout 6db 6db 6db enc r/c vcrvout 6db vcr cvbs/y tv cvbs vcr r/c enc cvbs/y encc encg vcrg encb vcrb enc y encrc vcrvin tvvin vcrrc enc v ( typical connection ) tv scar t vcr scart ( typical connection ) vvd2 vvss1 vvd1 monitor vvss2 6db video block monitor vcr fb tvfb 6db 0v 2v tvsb vcrsb 0/ 6/ 12v 0/ 6/ 12v vcrfb ( typical connection ) tv scart vcr scart ( typical connection ) int video blanking block
asahi kasei [AK4707] ms0551-e-00 2006/10 - 4 - ? ordering guide AK4707eq ? 10 +70 c 48pin lqfp (0.5mm pitch) ? pin layout tst2 tvfb 1 vvd1 48 2 vvss 3 tvvout 4 vvd2 5 tvrc 6 7 tvg 8 tvb 9 encb 10 encg 11 vcrvout 47 tst1 46 pdn 45 sda 44 scl 43 ainl+ 42 ainl- 41 ainr+ 40 ainr- 39 vd 38 encv 13 ency 14 tvvin 15 vcrvin 16 vcrfb 17 vcrrc 18 vcrg 19 vcrb 20 int 21 vcrsb 22 tvsb 23 35 34 33 32 31 30 29 28 27 26 25 dvcom vp vcroutl vcroutr tst3 tvinl tst4 tvoutl tvoutr tvinr vcrinl AK4707eq top view encrc 12 vcrinr 24 36 pvcom vss 37 encc
asahi kasei [AK4707] ms0551-e-00 2006/10 - 5 - ? main difference between ak4702 and AK4707 items ak4702 AK4707 dac x - audio mono input/ output x - video rgb video gain control x - tv/vcr video input monitor - x vcr slow blanking monitor in output mode. enabled disabled tv/vcr cvbs input detection & power save mode - x rf modulator output x - vcr y output x - bi-directional control for v c r-red/chroma x pinout pin#1 vcrc tst2 pin#28 monoin nc pin#33 monoout nc pin #39 ~ #42 i/f for dac amp input pin#46 rfv tst1 i 2 c speed (max) 100khz 400khz mask bits for int function (09h) - x others fb/sb loop back in auto mode. - x -: not available. x: available
asahi kasei [AK4707] ms0551-e-00 2006/10 - 6 - pin/function no. pin name i/o function 1 tst2 i test mode input pin #2 internal pull down 100k ? normally connected to vss. 2 vvss - video ground pin , 0v 3 tvvout o composite/luminance output pin for tv 4 vvd2 - video power supply pin #2: 5v normally connected to vvss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 5 tvrc o red/chrominance output pin for tv 6 tvg o green output pin for tv 7 tvb o blue output pin for tv 8 vvd1 - video power supply pin #1: 5v normally connected to vvss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 9 encb i blue input pin for encoder 10 encg i green input pin for encoder 11 encrc i red/chrominance input pin #1 for encoder 12 encc i chrominance input pin #2 for encoder 13 encv i composite/luminance input pin #1 for encoder 14 ency i composite/luminance input pin #2 for encoder 15 tvvin i composite/luminance input pin for tv 16 vcrvin i composite/luminance input pin for vcr 17 vcrfb i fast blanking input pin for vcr 18 vcrrc i red/chrominance input pin for vcr 19 vcrg i green input pin for vcr 20 vcrb i blue input pin for vcr 21 int o interrupt pin for video blanking 22 vcrsb i/o slow blanking input/output pin for vcr 23 tvsb o slow blanking output pin for tv 24 vcrinr i rch vcr audio input pin 25 vcrinl i lch vcr audio input pin 26 tvinr i rch tv audio input pin 27 tvinl i lch tv audio input pin 28 tst3 - test mode input pin #3 this pin should be connected to vss. 29 vcroutr o rch analog output pin #1 30 vcroutl o lch analog output pin #1 31 tvoutr o rch anal og output pin #2 32 tvoutl o lch analog output pin #2 33 tst4 - test mode input pin #4 this pin should be connected to vss. 34 vp - power supply pin, 12v normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 35 dvcom o audio common voltage pin #1 normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 36 pvcom o audio common voltage pin #2 normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. the caps affect the settling time of audio bias level. 37 vss - ground pin , 0v
asahi kasei [AK4707] ms0551-e-00 2006/10 - 7 - pin/function (continued) no. pin name i/o function 38 vd - power supply pin, 5v normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 39 ainr ? i rch negative analog input pin 40 ainr+ i rch positive analog input pin 41 ainl ? i lch negative analog input pin 42 ainl+ i lch positive analog input pin 43 scl i control data clock pin 44 sda i/o control data pin 45 pdn i power-down mode pin when at ?l?, the AK4707 is in the power-down mode and is held in reset. the AK4707 should always be reset upon power-up. 46 tst1 i test mode input pin #1 internal pull down 100k ? normally connected to vss 47 vcrvout o composite/luminance output pin for vcr 48 tvfb o fast blanking output pin for tv note: all digital input pins should not be left floating.
asahi kasei [AK4707] ms0551-e-00 2006/10 - 8 - internal equivalent circuit pin no. pin name type equivalent circuit description 43 45 scl pdn digital in vd 200 vss 39 40 41 42 ainr- ainr+ ainl ? ainl+ audio in vd 150k vss 44 sda digital i/o vd vss 200 i2c bus voltage must not exceed vd. 21 int digital out v ss vvd1 normally connected to vd(5v) through 10k ? resister externally. 3 5 6 7 47 48 tvvout tvrc tvg tvb vcrvout tvfb video out vvd2 vvss vvd2 vvss
asahi kasei [AK4707] ms0551-e-00 2006/10 - 9 - pin no. pin name type equivalent circuit description 9 10 11 12 13 14 15 16 17 18 19 20 encb encg encrc encc encv ency tvvin vcrvin vcrfb vcrrc vcrg vcrb video in vvd1 200 vvss 22 23 vcrsb tvsb video sb vp vvss vp vvss vvss 200 (120k) the 120k ? is not attached for tvsb. 24 25 26 27 vcrinr vcrinl tvinr tvinl audio in vp 150k vss 29 30 31 32 vcroutr vcroutl tvoutr tvoutl audio out vp vss vp vss 100 35 36 dvcom pvcom vcom out vd vss vd vss 100 vd vss
asahi kasei [AK4707] ms0551-e-00 2006/10 - 10 - absolute maximum ratings (vss =vvss = 0v; note 1) parameter symbol min max units power supply (note 2) vd vvd1 vvd2 vp ? 0.3 ? 0.3 ? 0.3 ? 0.3 6.0 6.0 6.0 14 v v v v input current (any pins except for supplies) iin - 10 ma input voltage vind ? 0.3 vd+0.3 v video input voltage vinv ? 0.3 vvd1+0.3 v audio input voltage (vcrinr/l, tvinr/l pins) vina1 ? 0.3 vp+0.3 v audio input voltage (ainl+/ ? , ainr+/ ? pins) vina2 ? 0.3 vd+0.3 v ambient operating temperature ta ? 10 70 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. vss and vvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes.
asahi kasei [AK4707] ms0551-e-00 2006/10 - 11 - recommended operating conditions (vss = vvss = 0v; note 1) parameter symbol min typ max units power supply (note 3) vd vvd1 vvd2 vp 4.75 4.75 4.75 11.4 5.0 5.0 5.0 12 5.25 5.25 vvd1 12.6 v v v v note 1. all voltages with respect to ground. note 3. vvd1 and vvd2 must be connected to the same voltage. *akm assumes no responsibility for the usage beyond the conditions in this datasheet. electrical characteristics (ta = 25 c; vp = 12v, vd = 5v; vvd1 = vvd2 = 5v) power supplies min typ max units power supply current normal operation (pdn = ?h?) (note 4) vd vvd1+vvd2 vp power-down mode (pdn = ?l?) (note 5) vd vvd1+vvd2 vp 10 20 5 10 10 10 20 40 10 100 100 100 ma ma ma a a a note 4. stby bit = ?0?, all video outputs active. no signal, no load for a/v switches. note 5. all digital inputs are held at vss. digital characteristics (ta = 25 c; vd = 4.75 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.0 - - - - 0.8 v v low-level output voltage (sda pin: iout= 3ma, int pin: iout= 1ma) vol - - 0.4 v input leakage current iin - - 10 a
asahi kasei [AK4707] ms0551-e-00 2006/10 - 12 - analog characteristics (audio) (ta = 25 c; vp = 12v, vd = 5v; vvd1 = vvd2 = 5v; signal frequency = 1khz; measurement frequency = 20hz 20khz; r l 4.5k ? ; 0db=2vrms output; unless otherwise specified) parameter min typ max units analog input: (tvinl/tvinr/vcrinl/vcrinr pins) analog input characteristics input voltage 2.0 vrms input resistance 100 150 - k ? analog input: (ainl+/ainl-/ainr-/ainr+ pins) analog input characteristics input voltage 1.0 vrms input resistance 100 150 - k ? stereo/mono output: (tvoutl/tvoutr/vcroutl/vcroutr pi ns) (note 6) analog output characteristics volume#0 step width 2.3 3.0 3.7 db thd+n (at 2vrms output) (note 7) ? 86 -80 db dynamic range ( ? 60db output, a-weighted) (note 7) 92 96 db s/n (a-weighted) (note 7) 92 96 db interchannel isolation (note 7,note 8) 80 90 db interchannel gain mismatch (note 7,note 8) - 0.3 - db gain drift - 200 - ppm/ c load resistance (ac-lord, note 10) tvoutl/r, vcroutl/r 4.5 k ? load capacitance tvoutl/r, vcroutl/r 20 pf output voltage 1.85 2 2.15 vrms frequency response 0 20.0khz 0.5 db power supply rejection (psr) (note 9) - 50 db note 6. measured by audio precision system two cascade. note 7. analog in to tvout. path : ainl+/ ? tvoutl, ainr+/ ? ? tvoutr note 8. between tvoutl and tvoutr with analog inputs ainl+/-, ainr+/-, 1khz/0db. note 9. the psr is applied to vd with 1khz, 100mv. note 10. thd+n: -80db(min. at 2vrns)
asahi kasei [AK4707] ms0551-e-00 2006/10 - 13 - analog characteristics (video) (ta = 25 c; vp = 12v, vd= 5v; vvd1 = vvd2 = 5v; unless otherwise specified.) parameter conditions min typ max units sync tip clamp voltage at output pin. 0.7 v chrominance bias voltage at output pin. 2.2 v gain input = 0.3vp-p, 100khz 5.5 6 6.5 db interchannel gain mismatch tvrc, tvg, tvb. input = 0.3vp-p, 100khz. -0.5 - 0.5 db frequency response input=0.3vp-p, 100khz to 6mhz -1.0 1.0 db input impedance chrominance input (internally biased) 40 60 - k ? input signal f = 100khz, maximum with distortion < 1.0% - - 1.5 vpp load resistance (note 11) 150 - - ? load capacitance c1 (note 11) c2 (note 11) 400 15 pf pf dynamic output signal f = 100khz, maximum with distortion < 1.0% - - 3 vpp y/c crosstalk f = 4.43mhz, 1vp-p input. among tvvout, tvrc and vcrvout outputs. - ? 50 - db s/n reference level = 0.7vp-p, ccir 567 weighting. bw = 15khz to 5mhz. - 74 - db differential gain 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - 0.3 - % differential phase 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - 0.3 - degree note 11. refer the figure 1. video signal output 75 ohm 75 ohm max: 400pf c1 r1 r2 max: 15pf c2 figure 1. load resistance r1+r2 and load capacitance c1/c2.
asahi kasei [AK4707] ms0551-e-00 2006/10 - 14 - switching characteristics (ta = 25 c; vp = 11.4 12.6v, vd = 4.75 5.25v, vvd1 = vvd2 = 4.75 5.25v) parameter symbol min typ max units control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note 12) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf reset timing pdn pulse width (note 13) tpd 150 ns note 12. data must be held for sufficient tim e to bridge the 300 ns transition time of scl. note 13. the AK4707 should be reset by pdn pin = ?l? upon power up. note 14. i 2 c is a registered trademark of philips semiconductors.
asahi kasei [AK4707] ms0551-e-00 2006/10 - 15 - ? timing diagram thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing tpd vil pdn power-down timing
asahi kasei [AK4707] ms0551-e-00 2006/10 - 16 - operation overview 1. system reset and power-down options the AK4707 should be reset once by bringing pdn pin = ?l ? upon power-up. the AK4707 has several operation modes. the pdn pin, auto bit, bias bit, stby bit and amp bit control operation modes as shown in table 1 and table 2. mode pdn pin auto bit stby bit bias bit mode 0 ?l? * * * full power-down 1 ?h? 1 * * auto startup mode (power-on default) 2 ?h? 0 1 1 standby & mute 3 ?h? 0 1 0 standby 4 ?h? 0 0 1 mute (amp power down) 5 ?h? 0 0 0 normal operation (amp operation) table 1. operation mode settings (*: don?t care) mode register control audio bias level video output tvfb, tvsb vcrsb 0 full power-down not available no video input power down hi-z hi-z pull-down (1) 1 auto startup mode (power-on default) video input (2) active active 2 standby & mute power down 3 standby active 4 mute (amp power down) power down 5 normal operation (amp operation) available active (3) hi-z / active active active note 15. internally pulled down by 120k ? (typ) resistor. note 16. video input to tvvin or vcrvin. note 17. tvoutl/r are muted by mute bit in the default state. table 2. status of each operation modes
asahi kasei [AK4707] ms0551-e-00 2006/10 - 17 - ? full power-down mode the AK4707 should be reset once by bringing pdn pin = ?l? upon power-up. pdn pin: power down pin l: device power down. h: normal operation. ? auto startup mode after when the pdn pin is set to ?h?, the AK4707 is in the auto startup mode. in this mode, all blocks except for the video detection circuit are powered down. once the video detecti on circuit detects video signal from tvvin pin or vcrvin pin, the AK4707 goes to the stand-by mode automatically a nd sends ?h? pulse via int pin. the sources of tvoutl/r are fixed to vcrinl/r, the sources of vcroutl/r are fixed to tvinl/r resp ectively. the source of dc- restore circuit is vcrvin pin. to exit the auto startup mode, set the auto bit to ?0?. auto bit (00h d3): auto startup bit 0: auto startup disable. (manual startup) 1: auto startup enable. (default) ? bias mode when the bias bit = ?1?, the bias voltage on the audio output goes to gnd level. bringing bias bit to ?0? changes this bias voltage smoothly from gnd to vp/2 by 2sec (typ.). this removes the huge click noise re lated the sudden change of bias voltage at power-on. the change of bias bit from ?1? to ?0? also makes smooth transient from vp/2 to gnd by 2sec (typ). this removes the huge click noise related the sudden change of bias voltage at power-off. bias bit (00h d1): bias-off bit 0: normal operation. 1: set the audio bias to gnd. (default) ? standby mode when the auto bit = bias bit = ?0? and the stby bit = ?1?, the AK4707 is forced into tv-vcr loop through mode. in this mode, the sources of tvoutl/r pins are fixed to vcrinl/r pins; the sources of vcroutl/r are fixed to tvinl/r pins respectively. all register values themselves are not changed by stby bit = ?1?. stby bit (00h d0): standby bit 0: normal operation. 1: standby mode. (default)
asahi kasei [AK4707] ms0551-e-00 2006/10 - 18 - ? normal operation mode to change analog switches, set the auto bit, bias bit and stby bit to ?0?. the AK4707 is in power-down mode until pdn pin = ?h?. the figure 2 shows an example of the system timing at the power-down and power-up by pdn pin. ? typical operation sequence (auto setup mode) figure 2 shows an example of the system timing at auto setup mode. pdn pin a udio out (dc) tvvout, vcrvout active (loop-through) tvvin signal in no signal don?t care signal in no signal don?t care vcrvin signal in no signal don?t care don?t care active (loop-through) hi-z hi-z active (loop-through) (gnd) active (loop-through) no signal no signal hi-z low power mode low power mode low power mode figure 2. typical operating sequence (auto setup mode) ? typical operation sequence (except auto setup mode) figure 3 shows an example of the system timing at auto setup mode. pdn p in ?1? (default) stby bit ?0? ?1? ?1? (default) bias bit ?0? ?stand-by? ?1? ?0? ?stand-by? ?mute? tv out amp tv-source select vcr in vcr in vcr in (1) vcr in fixed to vcr in(loop-through) (default) ?1? (default) a uto bit ?0? amp amp fixed to vcr in(loop-through) ?1? (2) notes: (1) set the stby bit = ?0? to pass for 20.2ms after set the mute bit = ?0?, to prevent the click noise (1). (2) mute the analog outputs externally if click noise (2) affects the system. figure 3. typical operating sequence (except auto setup mode)
asahi kasei [AK4707] ms0551-e-00 2006/10 - 19 - 2. audio block ? switch control the AK4707 has switch matrixes designed primarily for scart routing. those are controlled via the control register as shown in, table 3 and table 4 (please refer to the block diagram). (01h: d1-d0) tv1 tv0 source of tvoutl/r 0 0 amp 0 1 vcrin (default) 1 0 mute 1 1 (reserved) table 3. tvout switch configuration (01h: d5-d4) vcr1 vcr0 source of vcroutl/r 0 0 amp 0 1 tvin (default) 1 0 mute 1 1 (reserved) table 4. vcrout switch configuration ? volume control #0 (7-level volume) the AK4707 has a 7-level volume control (volume #0) as shown in table 5. the volume reflects the change of register value immediately. figure 4. volume #0(volume gain=0db:default), full differential stereo input (02h: d5-d3) l2 l1 l0 volume #0 gain output level (typ) 1 1 1 +12db 2vrms (with 0.5vrms differential input) 1 1 0 +9db - 1 0 1 +6db 2vrms (with 1vrms differential input) 1 0 0 +3db - 0 1 1 0db 2vrms (with 2vrms differential input: default) 0 1 0 -3db - 0 0 1 -6db 1vrms (with 2vrms differential input) 0 0 0 mute - table 5. volume #0, full differential stereo input 2vrms differential input tvoutl/r (vcroutl/r) a inl/r+ a inl/r- volume gain 0db volume #0 1vrms 1vrms 2vrms 0.47 0.47
asahi kasei [AK4707] ms0551-e-00 2006/10 - 20 - figure 5. volume #0(volume gain=0db:default), single-ended input (02h: d5-d3) vol2 vol1 vol0 volume #0 gain output level (typ) 1 1 1 +12db 2vrms (with 0.5vrms input) 1 1 0 +9db - 1 0 1 +6db 2vrms (with 1vrms input) 1 0 0 +3db - 0 1 1 0db 1vrms (with 1vrms input: default) 0 1 0 -3db - 0 0 1 -6db 0.5vrms (with 1vrms input) 0 0 0 mute - table 6. volume #0, single-ended input ? mute control to minimize the click noise at setting the mute bit = ?1?, the AK4707 has a zero-cross detection. when the zero bit = ?1?, the zero-cross detection function is enabled. tvoutl/r outputs analog common voltage at the input signal first zero-cross point from setting the mute bit = ?1? or when the zero-cross is not de tected within the time set by ztm1-0 bits (12.8msec to 102.4msec). tvoutl/r outputs of tv1-0 sw itch at the input signal firs t zero-cross point from setting the mute bit = ?0? or when the zero-cross is not detected within the time set by ztm1-0 bits. the zero-cross is detected on l/r channels at the tv1/0 selector independently. to disable this function, set the zero bit to ?0?. zero: zero-cross detection enable for tv1/0 selector 0: disable 1: enable (default) a inl/r+ a inl/r- tvoutl/r (vcroutl/r) volume gain 0db volume #0 1vrms 1vrms 0.47 0.47
asahi kasei [AK4707] ms0551-e-00 2006/10 - 21 - 3. video block ? video switch control the AK4707 has switches for tv and vcr. each switch can be controlled via registers independently. when auto bit = ?1? or stby bit = ?1?, these switches setting is ignored and set to fixed configuration (loop-through mode). refer the auto setup mode and standby mode. (04h: d2-d0) mode vtv2-0 bit source of tvvout pin source of tvrc pin source of tvg pin source of tvb pin shutdown 000 (hi-z) (hi-z) (hi-z) (hi-z) encoder cvbs /rgb 001 encv pin (encoder cvbs) encrc pin (encoder red,c) encg pin (encoder green) encb pin (encoder blue) encoder y/c 1 010 encv pin (encoder y) encrc pin (encoder c) hi-z (hi-z) encoder y/c 2 011 ency pin (encoder y) encc pin (encoder c) hi-z (hi-z) vcr (default) 100 vcrvin pin (vcr cvbs) vcrrc ?8= (vcr red,c) vcrg pin (vcr green) vcrb pin (vcr blue) tv cvbs 101 tvvin pin (tv cvbs) (hi-z) (hi-z) (hi-z) (reserved) 110 - - - - (reserved) 111 - - - - table 7. tv video output (refer note 18.) (04h: d5-d3) mode vvcr2-0 bit source of vcrvout pin shutdown 000 (hi-z) encoder cvbs or y/c 1 001 encv pin (encoder cvbs) encoder cvbs or y/c 2 010 ency pin (encoder cvbs) tv cvbs (default) 011 tvvin pin (tv cvbs) vcr 100 vcrvin pin (vcr cvbs) (reserved) 101 - (reserved) 110 - (reserved) 111 - table 8. vcr video output (refer note 18.) note 18. when input the video si gnal via encrc pin or vcrrc pin, se t clamp1-0 bits respectively.
asahi kasei [AK4707] ms0551-e-00 2006/10 - 22 - ? video output control (05h: d6-d0) each video output can be set to hi-z individually via contro l registers. these settings are ignored when the auto bit = ?1?. tvv: tvvout output control tvr: tvrcout output control tvg: tvgout output control tvb: tvbout output control vcrv: vcrvout output control tvfb: tvfb output control 0: hi-z. (default) 1: active. ? clamp and dc-restore circuit control (06h: d6-d5, d3-d2) each cvbs and y input has the sync tip clamp circuit. the sy nc tip voltage at each output is 0.7v (typ). this corresponds 0.35v (typ) at the scart connector when matched by 75 ? resistors. the clamp1-0 bits select the input circuit for encrc pin (encoder red/chroma) and vcrrc pin (vcr red/chroma) respectively. vclp1-0 bits select the source of dc-restore circuit. clamp1: encoder red/chroma (e ncrc pin) input clamp control 0: dc restore clamp active (for red signal. default) 1: biased (for chroma signal) clamp0: vcr r/c (vcrrc pin) input clamp control 0: dc restore clamp active (for red signal) 1: biased (for chroma signal. default) vclp1-0: dc restore source control when the auto bit = ?1?, the source is fixed to vcrvin. vclp1 bit vclp0 bit sync source of dc restore 0 0 encv (default) 0 1 ency 1 0 vcrvin 1 1 (reserved) table 9. dc restore source control
asahi kasei [AK4707] ms0551-e-00 2006/10 - 23 - 4. blanking control the AK4707 supports fast blanking signals and slow bl anking (function switching) signals for tv/vcr scart. ? input/output control for fast/slow blanking fb1-0: tv fast blanking output control (07h: d1-d0) fb1 bit fb0 bit tvfb pin output level 0 0 0v (default) 0 1 2v<, 4v(typ) at 150 ? load 1 0 same as vcr fb input (4v/0v) 1 1 (reserved) table 10. tv fast blanking output (note: minimum load is 150 ? ) sbt1-0: tv slow blanking output control (07h: d3-d2) sbt1 bit sbt0 bit tvsb pin output level 0 0 < 2v (default) 0 1 5v <, < 7v 1 0 (reserved) 1 1 10v < table 11. tv slow blanking output (note: minimum load is 10k ? ) sbv1-0: vcr slow blanking output control (07h: d5-d4) sbv1 bit sbv0 bit vcrsb pin output level 0 0 < 2v (default) 0 1 5v <, < 7v 1 0 (reserved) 1 1 10v < table 12. vcr slow blanking output (note: minimum load is 10k ? ) sbio1-0: tv/vcr slow blanking i/o control (07h: d7-d6) sbio1 bit sbio0 bit vcrsb pin direction tvsb pin direction 0 0 output (controlled by sbv1-0 bits) output (controlled by sbt1-0 bits) (default) 0 1 (reserved) (reserved) 1 0 input (stored in svcr1-0 bits) output (controlled by sbt1-0 bits) 1 1 input (stored in svcr1-0 bits) output (same output as vcr sb) table 13. tv/vcr slow blanking i/o control
asahi kasei [AK4707] ms0551-e-00 2006/10 - 24 - 5. monitor options and int function ? monitor options (08h: d4-d0) the AK4707 has several detection functions. svcr1-0 bits, fvcr bit, vcmon bit and tvmon bit reflect the input dc level of vcr slow blanking, the input dc level of vcr fast blanking and signals input to tvvin or vcrvin pins. svcr1-0: vcr slow blanking status monitor svcr1-0 bits reflect the voltage at vcrsb pin only when the vcrsb is in the input mode. when the vcrsb is in the output mode, svcr1-0 bits hold previous value. vcrsb pin input level svcr1 bit svcr0 bit < 2v 0 0 4.5v to 7v 0 1 (reserved) 1 0 9.5v < 1 1 table 14. vcr slow blanking monitor fvcr: vcr fast blanking input level monitor this bit is enabled when tvfb bit = ?1?. vcrfb pin input level fvcr bit < 0.4v 0 1v < 1 table 15. vcr fast blanking monitor (typical threshold is 0.7v) vcmon: vcrvin pin video input monitor (mcomn bit = ?1?), tvvin pin or vcrvin pin video input monitor (mcomn bit = ?0?) 0: no video signal detected. 1: detects video signal. tvmon: tvvin pin video input monitor (active when mcomn bit = ?1?) 0: no video signal detected. 1: detects video signal. auto (00h d3) mcomn (09h d7) tvvin signal vcrvin signal tvmon (08h d4) vcmon (08h d3) 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 1 1 1 1 * 0 0 0 0 1 * 0 1 0 1 1 * 1 0 0 1 1 * 1 1 0 1 *:don?t care, note 19. tvvin/vcrvin signal: signal 0 = no signal applied, signal 1 = signal applied table 16. tv/vcr monitor function
asahi kasei [AK4707] ms0551-e-00 2006/10 - 25 - ? int function and mask options (09h: d3-d1) changes of the 08h status can be monitored via the int pin. the int pin is the open drain output and goes ?l? for 2 s (typ.) when the status of 08h is changed. this pin should be connected to vd (typ. 5v) through 10kohm resistor. mtv bit, mvc bit, mcomn bit, mfvcr bit and msvcr bit control the reflection of the status change of these monitors onto the int pin from report to prevent to masks each monitor. AK4707 r=10k ? int vd up figure 6. int pin mvc: vcmon mask. refer table 18 mtv: tvmon mask. refer table 17 mcomn: refer table 16 auto (00h d3) tvmon (08h d4) mtv (09h d4) int 0 no change 0 hi-z 0 no change 1 hi-z 0 change 0 generates ?l? pulse 0 change 1 hi-z 1 no change 0 hi-z 1 no change 1 hi-z note 20. when the stby bit = ?0?, the tv monitor mask function is enabled. note 21. when auto bit = ?1?, tvmon does not change. table 17. tv monitor mask auto (00h d3) vcmon (08h d3) mvc (09h d3) int 0 no change 0 hi-z 0 no change 1 hi-z 0 change 0 generates ?l? pulse 0 change 1 hi-z 1 no change 0 hi-z 1 no change 1 hi-z 1 change 0 generates ?l? pulse 1 change 1 generates ?l? pulse note 22. when the stby bit = ?0?, the vcr monitor mask function is enabled. table 18. vcr monitor mask mfvcr: fvcr monitor mask. 0: change of fvcr is reflected to int pin. (default) 1: change of fvcr is not reflected to int pin. msvcr: svcr1-0 monitor mask 0: change of svcr1-0 is reflected to int pin. (default) 1: change of svcr1-0 is not reflected to int pin.
asahi kasei [AK4707] ms0551-e-00 2006/10 - 26 - 6. control interface i 2 c-bus control mode 1. write operations figure 7 shows the data transfer sequence in i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition (figure 13). after the start condition, a slave address is sent. this address is 7bits long followed by an eighth bit that is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as ?0010001?. if the slave address match that of the AK4707, the AK4707 generates the acknowledge and the opera tion is executed. the master must generate the acknowledge-related clock pulse and release the sda line (h igh) during the acknowledge clock pulse (figure 15). a ?1? for r/w bit indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the address for control registers of the AK4707. the format is msb first, and those most significant 3-bits are fixed to zeros (figure 9). the data after the second byte contain control data. the format is msb first, 8bits (figure 10). the AK4707 generates an acknowledge after each byte has been r eceived. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition (figure 13). the AK4707 can execute multiple one byte write operations in a sequence. after receipt of the third byte, the AK4707 generates an acknowledge, and awaits the next data again. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is tran sferred. after the receipt of each data, the internal address counter is incremented by one, and the ne xt data is taken into next address au tomatically. if the address exceeds 09h prior to generating the stop condition, the addr ess counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (figure 15) except for the start and the stop condition. sda s t a r t a c k a c k s slave a ddress a c k sub a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k figure 7. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 0 1 r/w figure 8. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 9. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 10. byte structure after the second byte
asahi kasei [AK4707] ms0551-e-00 2006/10 - 27 - 2. read operations set r/w bit = ?1? for read operations. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of termin ating the write cycle after the receipt th e first data word. after the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 09h prior to generating the stop conditi on, the address counter will ?roll over? to 00h and the previous data will be overwritten. the AK4707 supports two basic read operati ons: current address read and random read. 2-1. current address read the AK4707 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the AK4707 generates an acknowledge, transmits 1byte data which address is set by the in ternal address counter and increments the internal address counter by 1. if the master does not ge nerate an acknowledge to the data but generate the stop condition, the AK4707 discontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n+1) p s t o p data(n+x) a c k data(n+2) a c k r/w= ?1? a c k data(n) figure 11. current address read 2-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start condition, slave address (r/w bit = ?0?) and then the register address to read. after the register?s address is acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to ?1?. then the AK4707 generates an acknowledge, 1-byte data and increments the internal addr ess counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the AK4707 disc ontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k sub a ddress(n) s t a r t a c k s slave a ddress r/w= ?1? figure 12. random address read
asahi kasei [AK4707] ms0551-e-00 2006/10 - 28 - scl sda stop condition start condition s p figure 13. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 14. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 15. bit transfer on the i 2 c-bus
asahi kasei [AK4707] ms0551-e-00 2006/10 - 29 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 0 0 0 0 auto 0 bias stby 01h switch mute 0 vcr1 vcr0 mono 0 tv1 tv0 02h main volume 0 0 l2 l1 l0 1 1 1 03h zerocross 0 vmono 0 0 0 zero ztm1 ztm0 04h video switch 0 0 vvcr2 vvcr1 vvcr0 vtv2 vtv1 vtv0 05h video output enable 0 tvfb 0 vcrv tvb tvg tvr tvv 06h video clamp 0 vclp1 vclp0 0 clamp1 clamp0 0 0 07h s/f blanking control sbio1 sbio0 sbv1 sbv0 sbt1 sbt0 fb1 fb0 08h s/f blanking monitor 0 0 0 tvmon vcmon fvcr svcr1 svcr0 09h monitor mask mcomn 0 0 mtv mvc mfvcr msvcr 0 when the pdn pin goes ?l?, the registers are initialized to their default values. while the pdn pin = ?h?, all registers can be accessed. do not write any data to the register over 09h. ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 0 0 0 0 auto 0 bias stby r/w r/w default 0 0 0 0 1 0 1 1 stby: standby control 0: normal operation 1: standby mode (default). a ll registers are not initialized. source of tvout : fixed to vcrin, source of vcrout : fixed to tvin source of tvvout : fixed to vcrvin (or hi-z), source of tvrc : fixed to vcrrc (or hi-z), source of tvg : fixed to vcrg (or hi-z), source of tvb : fixed to vcrb (or hi-z), source of vcrvout : fixed to tvvin (or hi-z), source of tvfb : fixed to vcrfb (or hi-z), source of tvsb : fixed to vcrsb. bias: audio output control 0: normal operation 1: all audio outputs to gnd (default) auto: auto startup bit 0: auto startup disable (manual startup). 1: auto startup enable (default). note 23. when the sbio1 bit = ?1?( default = ?0?), the change of auto bit may cause a ?l? pulse on int pin.
asahi kasei [AK4707] ms0551-e-00 2006/10 - 30 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h switch mute 0 vcr1 vcr0 mono 1 tv1 tv0 r/w r/w default 1 0 0 1 0 1 0 1 tv1-0: tvoutl/r pins source switch 00: amp 01: vcrinl/r pins (default) 10: mute 11: reserved mono: mono select for tvoutl/r pins 0: stereo. (default) 1: mono. (l+r)/2 vcr1-0: vcroutl/r pins source switch 00: amp 01: tvinl/r pins (default) 10: mute 11: reserved mute: mute switch 0: normal operation 1: mute (default) when mute bit = ?1?, tvoutl/r outputs vcom voltage after tvoutl/r output is zero-crossing (zero bit= ?1?). set the mute bit= ?1? to pass for 100ms after setting the pdn pin=?h?. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h main volume 0 0 l2 l1 l0 1 1 1 r/w r/w default 0 0 0 1 1 1 1 1 l2-0: volume #0 control those registers control both lch and rch of volume #0. 111: volume gain = +12db 110: volume gain = +9db 101: volume gain = +6db 100: volume gain = +3db 011: volume gain = +0db (default) 010: volume gain = -3db 001: volume gain = -6db 000: mute
asahi kasei [AK4707] ms0551-e-00 2006/10 - 31 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h zerocross 0 vmono 0 0 0 zero ztm1 ztm0 r/w r/w default 0 0 0 0 0 1 0 0 ztm1-0: the time length control of zero-cross timeout 00: typ. 12.8ms, max. 20.2ms (default) 01: typ. 25.6ms 10: typ. 51.2ms 11: typ. 102.4ms zero: zero-cross detection enable for tvout output 0: disable the tvoutl/r outputs vcom voltage immediately without zero-cross when mute bit = ?1?. the tvoutl/r outputs of tv1-0 switch immediately without zero-cross when mute bit = ?0?. 1: enable (default) the tvoutl/r outputs vcom voltage when timeout or zero-cross before timeout when mute bit = ?1?. the tvoutl/r outputs of tv1-0 switch when timeout or zero-cross before timeout when mute bit = ?0?. vmono: mono select for vcroutl/r pins 0: stereo. (default) 1: mono. (l+r)/2
asahi kasei [AK4707] ms0551-e-00 2006/10 - 32 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h video switch 0 0 vvcr2 vvcr1 vvcr0 vtv2 vtv1 vtv0 r/w r/w default 0 0 0 1 1 1 0 0 vtv2-0: selector for tv video output refer the table 7. vvcr2-0: selector for vcr video output refer the table 8. addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h output enable 0 tvfb 0 vcrv tvb tvg tvr tvv r/w r/w default 0 0 0 0 0 0 0 0 tvv: tvvout output control tvr: tvrcout output control tvg: tvgout output control tvb: tvbout output control vcrv: vcrvout output control tvfb: tvfb output control 0: hi-z (default) 1: active.
asahi kasei [AK4707] ms0551-e-00 2006/10 - 33 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h video clamp 0 vclp1 vclp0 0 clamp1 clamp0 0 0 r/w r/w default 0 0 0 0 0 1 0 0 clamp1: encoder r/chroma (en crc pin) input clamp control 0: dc restore clamp active (for red signal. default) 1: biased (for chroma signal.) clamp0: vcr r/c (vcrc pin) input clamp control 0: dc restore clamp active (for red signal) 1: biased (for chroma signal. default.) vclp1-0: dc restore source control 00: encv pin (default) 01: ency pin 10: vcrvin pin 11: (reserved) when the auto bit = ?1?, the s ource is fixed to vcrvin pin. addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h s/f blanking sbio1 sbio0 sb v1 sbv0 sbt1 sbt0 fb1 fb0 r/w r/w default 0 0 0 0 0 0 0 0 fb1-0: tv fast blanking output control (for tvfb pin) 00: 0v (default) 01: 2v<, 4v(typ.) at 150 ? load 10: follow vcr fb input (4v/0v) 11: (reserved) sbt1-0: tv slow blanking output control (for tvsb pin. minimum load is 10k ? .) 00: < 2v (default) 01: 5v <, < 7v 10: (reserved) 11: 10v < sbv1-0: vcr slow blanking output control (for vcrsb pin. minimum load is 10k ? .) 00: < 2v (default) 01: 5v <, < 7v 10: (reserved) 11: 10v < sbio1-0: tv/vcr slow blanking i/o control refer the table 13.
asahi kasei [AK4707] ms0551-e-00 2006/10 - 34 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h sb/fb monitor 0 0 0 tvmon vcmon fvcr svcr1 svcr0 r/w read default 0 0 0 0 0 0 0 0 svcr1-0: vcr slow blanking status monitor svcr1-0 bits reflect the voltage at vcrsb pin only when the vcrsb is in the input mode. when the vcrsb is in the output mode, svcr1-0 bits hold previous value. vcrsb pin input level svcr1 bit svcr0 bit < 2v 0 0 4.5v to 7v 0 1 (reserved) 1 0 9.5v < 1 1 table 19. vcr slow blanking monitor fvcr: vcr fast blanking input level monitor this bit is enabled when tvfb bit = ?1?. vcrfb pin input level fvcr bit < 0.4v 0 1v < 1 table 20. vcr fast blanking monitor (typical threshold is 0.7v) vcmon: tvmon: refer the table 16. addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h monitor mask mcomn 0 0 mtv mvc mfvcr msvcr 0 r/w r/w default 0 0 0 0 1 0 0 0 msvcr: svcr1-0 bits monitor mask 0: the int pin reflects the cha nge of svcr1-0 bit. (default) 1: the int pin does not reflect the change of svcr1-0 bits. mfvcr: fvcr monitor mask 0: the int pin reflects the ch ange of fvcr bit. (default) 1: the int pin does not reflect the change of fvcr bit. mvc: vcr input monitor mask refer the table 18. mtv: tv input monitor mask refer the table 17. mcomn: monitor mask option refer the table 16 .
asahi kasei [AK4707] ms0551-e-00 2006/10 - 35 - system design figure 16 and figure 17 shows the system connection diagram example. an evaluation board is available which demonstrates application circuits, the optimum lay out, power supply arrangements and measurement results. tst2 tvfb 1 vvd1 2 vvss 3 tvvout 4vvd2 5tvrc 6 7 tvg 8 tvb 9 encb 10 encg 11 vcrvout tst1 pdn sd a scl ainl+ ainl- ainr+ ainr- vd 13 14 15 16 17 18 19 20 21 22 23 a k4707eq encrc 12 encv ency tvvin vcrvin vcrfb vcrrc vcrg vcrb int vcrsb tvsb vcrinr 24 35 34 33 32 31 30 29 28 27 26 25 36 dvcom vp vcroutl vcroutr tst3 tvinl tst4 tvoutl tvoutr tvinr vcrinl pvcom vss 48 47 46 45 44 43 42 41 40 39 38 37 encc 75 75 75 video 5v 0.1u 0.1u 0.1u 0.1u video encoder 0.1u 75 10u 0.1u + + mpeg micro controller 10u 0.1u + 10u 0.1u a udio 5v 0.47u 0.47u 0.47u 0.47u decoder dacl dacr 75 75 0.1u 0.1u 10u + + a nalog 12v + 10u + 10u 220k + 10u + 10u tv scart 220k 220k 220k 300 300 300 300 0.47u 300 0.47u 300 0.47u 300 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u vcr scart 300 0.47u 400 400 75 75 75 75 10u 10u 0.1u 75 75 75 75 75 75 75 75 a nalog ground + digital ground figure 16. typical connection diagram (full differential stereo input)
asahi kasei [AK4707] ms0551-e-00 2006/10 - 36 - tst2 tvfb 1 vvd1 2 vvss 3 tvvout 4vvd2 5tvrc 6 7 tvg 8 tvb 9 encb 10 encg 11 vcrvout tst1 pdn sd a scl ainl+ ainl- ainr+ ainr- vd 13 14 15 16 17 18 19 20 21 22 23 a k4707eq encrc 12 encv ency tvvin vcrvin vcrfb vcrrc vcrg vcrb int vcrsb tvsb vcrinr 24 35 34 33 32 31 30 29 28 27 26 25 36 dvcom vp vcroutl vcroutr tst3 tvinl tst4 tvoutl tvoutr tvinr vcrinl pvcom vss 48 47 46 45 44 43 42 41 40 39 38 37 encc 75 75 75 video 5v 0.1u 0.1u 0.1u 0.1u video encoder 0.1u 75 10u 0.1u + + mpeg micro controller 10u 0.1u + 10u 0.1u a udio 5v 0.47u 0.47u 0.47u 0.47u decoder dacl dacr 75 75 0.1u 0.1u 10u + + a nalog 12v + 10u + 10u 220k + 10u + 10u tv scart 220k 220k 220k 300 300 300 300 0.47u 300 0.47u 300 0.47u 300 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u vcr scart 300 0.47u 400 400 75 75 75 75 10u 10u 0.1u 75 75 75 75 75 75 75 75 a nalog ground digital ground + figure 17. typical connection diagram (single-ended input )
asahi kasei [AK4707] ms0551-e-00 2006/10 - 37 - ? grounding and power supply decoupling vd, vp, vvd1, vvd2, vss and vvss should be supplied fro m analog supply unit with low impedance and be separated from system digital supply. an electrolytic capacitor 10 f parallel with a 0.1 f ceramic capacitor should be attached to these pins to eliminate th e effects of high frequency noise. the 0.1 f ceramic capacitor should be placed as near to vd, vp, vvd1, vvd2 as possible. ? voltage reference each dvcom/pvcom are signal ground of this chip. an electrolytic capacitor 10 f parallel with a 0.1 f ceramic capacitor should be attached to these vcom pins to eliminat e the effects of high frequency noise. no load current may be drawn from these vcom pins. all signals, especially clocks, should be kept away from these vcom pins in order to avoid unwanted coupling into the AK4707. ? analog audio outputs the analog outputs are also single-ended and centered on 5.6v(typ.). the output signal range is typically 2vrms. the dc voltage on analog outputs are eliminated by ac coupling.
asahi kasei [AK4707] ms0551-e-00 2006/10 - 38 - ? external circuit example analog audio input pin tvinl/r vcrinl/r 0.47f 300ohm (cable) analog audio input pin a inr+ a in r - a inl+ a inl- 0.47f analog audio output pin tvoutl/r vcroutl/r 10f 300ohm total > 4.5kohm (cable) analog video input pin encv, ency, vcrvin, tvvin, encrc, encc, vcrrc, encg, vcrg, encb, vcrb 0.1f 75ohm (cable) 75ohm analog video output pin tvvout, tvrc tvg, tvr, tvb, vcrvout max 400pf 75ohm 75ohm max 15pf (cable)
asahi kasei [AK4707] ms0551-e-00 2006/10 - 39 - slow blanking pin tvsb vcrsb max 3nf (with 400ohm) 400ohm (max 500ohm) min: 10k ohm (cable) fast blanking input pin vcrfb 75ohm (cable) 75ohm fast blanking output pin tvfb 75ohm 75ohm (cable)
asahi kasei [AK4707] ms0551-e-00 2006/10 - 40 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48pin lqfp(unit:mm) 0.10 37 24 25 36 0.145 0.05 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 m 0.5 0.2 0.5 ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatmen t: solder (pb free) plate
asahi kasei [AK4707] ms0551-e-00 2006/10 - 41 - marking AK4707eq xxxxxxx 1 xxxxxxxx: date code identifier revision history date (yy/mm/dd) revision reason page contents 06/10/16 00 first edition
asahi kasei [AK4707] ms0551-e-00 2006/10 - 42 - important notice ? these products and their specificat ions are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any pat ent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulati ons of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system , and akm assumes no responsibility relating to any such use, except with the express written c onsent of the representative director of akm. as used here: (a) a hazard related device or system is one des igned or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expect ed to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform ma y reasonably be expected to result, whether directly or indirectly, in the lo ss of the safety or effectiveness of the device or system containing it, and which must therefor e meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who dist ributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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